(a) Field of the Invention
The present invention relates to a method for manufacturing a MOS (metal-oxide-semiconductor) transistor of a semiconductor device. More particularly, the present invention relates to a method for manufacturing a MOS transistor that prevents contact spiking (i.e., excessive etching) of a field oxidation film adjacent to a device region during etching to form contact holes. The present invention relates also to a semiconductor device employing a MOS transistor manufactured using the method of the present invention.
(b) Description of the Related Art
There are two general classes of field effect transistors (FETs) and they include the MOSFET and the JFET (junction FET). The present invention is related to the MOSFET. The MOSFET typically includes on a semiconductor substrate the electrodes of a source, a drain, and a gate. Metal interconnect lines are connected to upper areas of the source, drain, and gate to allow application (of electrical signals to the same, and the electrodes and the metal interconnect lines are electrically connected through contact formed at contact hole.
In order to minimize the resistance of each of the electrodes, silicide films are formed between the metal interconnect lines and each electrode of the source, drain, and gate. A silicon nitride film, which functions as an etching completion layer during etching to form contact holes, is deposited over an entire upper surface of the transistor that includes the silicide films.
FIGS. 1A to 1B are partial sectional views used to describe a conventional method for manufacturing a MOS transistor.
With reference to FIG. 1A, thermal oxidation of a silicon wafer 1, on which a device region is defined, is performed by a field oxidation film 2 using a LOCOS (local oxidation of silicon) or trench process such that a gate oxidation film 3 is grown on a surface of the device region of the silicon wafer 1. After depositing polysilicon, which will be used for gate electrodes 4, over an entire upper surface of the silicon wafer 1, the polysilicon and the gate oxidation layer 3 are patterned to a predetermined width.
Next, a p-type or n-type dopant is ion-injected at a low concentration on the device region of the silicon wafer 1 using a mask. As a result, LDDs (lightly doped drains) 5 are formed on the device region of the silicon wafer 1, as are side walls 6 to both sides of the gate oxidation film 3 and the gate electrode 4. Following this operation, a conducting dopant identical to that used for the LDDs 5 is ion-injected at a high concentration on the device region of the silicon wafer 1 using a mask to thereby form a source 7 and a drain 7.
Subsequently, titanium is deposited to a thickness of approximately 400Å over the entire surface of the silicon wafer 1 by a sputtering method, then RTP (rapid thermal processing) is performed for about 30 seconds and at a temperature of roughly 750 Å while injecting nitrogen at a flow rate of approximately 50 sccm . As a result, with reference to FIG. 1A, titanium suicide 8′ is formed by the reaction between titanium and silicon. The titanium on the side walls 6 and the field oxidation film 2 is not reacted and therefore remains as unreacted titanium.
The unreacted titanium is a metal and so may interfere with device operation. The unreacted titanium is therefore removed using a solvent. Also, in order to reduce the resistance of the suicide 8′ and increase the strength of the same, a heat process is performed in a nitrogen environment and at a temperature of approximately 910 Å.
After the above processes, in order to form a liner film that is used as an etching completion layer during etching to form contact holes, a silicon nitride film 9, with reference to FIG. 1A, is formed to a thickness of roughly 300 Å using plasma enhanced chemical vapor deposition (PECVD).
In the above process, the silicon nitride film 9 is less thickly deposited at depressed areas adjacent to the device region (one of which is circled using a dotted line in FIG. 1A) than in other areas. The depressed areas are formed as a result of structural problems occurring when forming the field oxidation film 2.
Next, an insulating layer, that is, a pre-metal dielectric (PMD) layer 10 is thickly formed by using atmospheric pressure chemical vapor deposition (APCVD) on the silicon nitride film 9, after which the PMD layer 10 is heat treated to improve the strength of the same. Chemical mechanical polishing (CMP) is then performed to flatten the PMD layer 10.
Subsequently, to prepare for the formation of contact holes, a photosensitive film pattern 11 is formed on the flattened PMD layer 10. With reference to FIG. 1B, exposed areas of the PMD layer 10 are then etched using the photosensitive film pattern 11 as a mask to thereby form contact holes 12.
Next, TiN 13 is then thinly deposited as a barrier metal film over the entire upper surface of the silicon wafer 1, after which tungsten 14 is used to fill the contact holes 12.
In the above conventional method for manufacturing a MOS transistor, the silicon nitride film 9, which is used as an etching completion layer, is not formed to a uniform thickness. As a result, when etching the PMD layer 10, the areas of the silicon nitride film 9 formed over the depressed areas of the field oxidation film 2 adjacent to the device region are more quickly etched than other areas of the silicon nitride film 9. Therefore, a contact spiking phenomenon occurs, in which the silicon nitride film 9 is over-etched past where the field oxidation film 2 (under these areas of the silicon nitride film 9) starts. One such area is circled using a dotted line in FIG. 1B. The contact spiking phenomenon ultimately results in the interference of the flow of current in the source 7 and the drain 7 such that the semiconductor device operates improperly.
Such a contact spiking phenomenon may also occur as a result of misalignment of the photosensitive film pattern 11 when forming the same to form the contact holes 12.